1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly, to a floating gate type EEPROM (Electrically Erasable and Programmable Read Only Memory) equipped with an erasing gate electrode and a method for fabricating the same.
2. Description of the Related Art
In recent years, a floating gate type EEPROM, as a nonvolatile semiconductor memory device capable of holding written information with no power supply, has been used for an internal and external memory device for a variety of computers.
Now, several kinds of structures of the floating gate type EEPROM are proposed. One of them is a structure in which an erasing gate electrode is provided in the vicinity of a floating gate (for example, see JP-A-4-340767). FIGS. 13A and 13B to FIGS. 18A and 18B and 18c are sequential step sectional views, in each of which figure A shows a section taken in line B-B' of figure B, and figure B shows a section taken in line A-A' in figure A. Incidentally, FIG. 18C is a view showing an peripheral region adjacent to the structure shown in FIG. 18B. In FIG. 18C, reference numeral 32S denotes an electric wiring pattern of a peripheral circuit formed in the same step as the erasing gate electrode 32.
First, as seen from FIGS. 13A and 13B, the one main surface of a P-type silicon (Si) 21 is selectively subjected to ion implantation to form N-type diffusion layers 22a and 22b. These N-type diffusion layers serve as a source and a drain of a memory cell, respectively.
As seen from FIGS. 14A and 14B, by a known CVD technique, a silicon oxide film 23 for element isolation is formed on the P-type Si substrate 21. By selective dry etching using a photoresist, a prescribed area of the silicon oxide film 23 is removed selectively. Subsequently, by the known CVD technique, another silicon oxide film is formed on the entire surface. Thereafter, by anisotropic dry etching, a side wall film 24 made of silicon oxide is formed on the side wall of the silicon oxide film 23.
As seen from FIGS. 15A and 15B, by a thermal oxidation technique, a silicon oxide film 25 serving as a gate oxide film is formed on the exposed area of the P-type Si substrate 21. Thereafter, by the known CVD technique, a polycrystalline silicon (poly-Si) film 26 is formed on the entire surface. Using the selective dry etching using photoresist, with a prescribed area of the poly-Si film 26 left, the remaining area is removed. This poly-Si film 26 serves as a floating gate electrode.
As seen from FIGS. 16A and 16B, by the thermal oxidation technique, a silicon oxide film 27 is formed on the entire surface. By the known CVD technique, a poly-Si film 28 is formed thereon. Thereafter, by the known CVD technique, a silicon oxide film 29 is formed, and further, using the selective dry etching using photoresist as a mask, with a prescribed area of the silicon-oxide film 29 left, the remaining area is removed. Subsequently, using as a mask the silicon oxide film 29, a prescribed area of the poly-Si film 28 and the silicon oxide film 27 is selectively removed subsequently. The poly-Si film 28 serves as a control gate electrode.
As seen from FIGS. 17A and 17B, by the known CVD technique, a silicon oxide film 30 is formed on the entire surface. Subsequently, by the anisotropic dry etching, a side wall film made of the silicon oxide film 30 is formed on the side wall of the silicon oxide film 29 and poly-silicon film 28. Thereafter, using as a mask the silicon oxide films 29 and 30, with a prescribed area of the underlying poly-Si film 26 being left, its remaining unnecessary portion is removed.
As seen from FIGS. 18A-18c, by the thermal oxidation technique, a silicon oxide film 31 serving as a tunnel film is formed on the exposed area of the side of the poly-Si film 26. Subsequently, by the known CVD technique, a poly-Si film 32 is formed. Further, by the selective dry etching technique using photoresist, with a prescribed pattern of the poly-Si film 32 being left, its remaining area is removed to form an erasing gate electrode made of the poly-Si film 32.
Further, metallic wirings (not shown) will be made for the N-type diffusion layers 22a and 22b serving as a source and a drain, the poly-Si film 28 serving as a control gate electrode and poly-Si film 32 serving as an erasing gate electrode.
An explanation will be given of the operation of the semiconductor memory device thus fabricated.
In a write operation, a voltage of 12 V is applied to the poly-Si film 28 serving as a control gate electrode, and the P-type Si substrate 21 and the N-type diffusion layer 22a serving as a source region are grounded. Simultaneously, a voltage pulse signal having a height of 10 V and width of 10.times.10.sup.-6 sec is applied to the N-type diffusion layer 22b serving as a drain region. Then, hot electrons are generated in the vicinity of the boundary between the N-type diffusion layer 22b and the P-type Si substrate 21. Part of them is pulled by the potential of the poly-Si film 26 which has been enhanced due to coupling so that they are injected into the poly-Si film 26 through the silicon oxide film 25. They remain stored in the poly-Si film 26 serving as a floating gate even after completion of application of the voltage pulses. Thus, the write operation is completed.
In an erase operation, with the poly-Si film 28 serving as the control gate electrode, P-type Si substrate 21, N-type diffusion layer 22a serving as the source region and N-type diffusion layer 22b being grounded, voltage pulses having a height of 15 V and width of 1.times.10.sup.-3 sec are applied to the poly-Si film 32 serving as the erasing gate electrode. During the application of the voltage pulses, the electrons which have been stored in the poly-Si film 26 serving as the floating gate electrode move to the poly-Si film 32 through the silicon oxide film 31. The electrons in the poly-Si film 26 are eventually discharged to complete the erasing operation.
In a read operation, with the P-type substrate 21 and N-type diffusion layer 22a serving as the source region being grounded, voltages of 5 V and 1.5 V are applied to the poly-Si film 28 serving as the control gate electrode and the N-type diffusion layer 22b serving as the drain region, respectively. In this state, a current flowing between the N-type diffusion layer serving as the drain region and the N-type diffusion layer 22a serving as the source region is read.
In the floating gate type EEPROM subjected to the write operation, when it serves as a MOS (Metal-Oxide-Silicon) transistor, the threshold voltage is boosted owing to the electrons stored in the floating gate electrode of the poly-Si film 26 so that the current flowing between the N-type diffusion layer 22b serving as the drain region and the N-type diffusion layer 22a serving as the source region becomes several pA or less. On the other hand, in the floating gate type EEPROM subjected to the erase operation, the threshold voltage is lowered as compared with when it is in the written state so that a current of several .mu.A-several tens of .mu.A flows by the above read operation.
Thus, in terms of the current flowing the N-type diffusion layer 22b serving as the drain region and the N-type diffusion layer 22a serving as the source region, the written state and erased state of the floating gate EEPROM can be discriminated from each other.
However, the conventional floating gate type EEPROM having an erasing gate electrode has the following defects. In such an EEPROM, on an element isolation film which is a CVD film formed on the surface of an Si substrate, the floating gate electrode, control gate electrode and erasing electrode are successively stacked. Therefore, when the floating gate electrode, control electrode and erasing gate electrode and erasing gate electrode are formed, a very large level difference occurs between each electrode and the surface of the Si substrate. Particularly, assurance of the depth of focus in lithography of the erasing gate electrode may become difficult, or etching remainder is apt to occur during the dry etching. This makes it difficult to effect micromachining less than submicron.